The transmission of multi-gigabit data rates in wired broadband communication systems pose a big challenge to system design. Part of the challenge lies in the design of the communication channel and interfacing to it. Typical issues that need to be dealt with are channel impedance matching and channel losses of the high frequency components of the signal due to channel parasitic impedances manifested in inductive, capacitive and skin loss among other effects.
Of a particular interest is matching of impedance between the data channel and the receiving end. In an ideal scenario, a termination resistance is placed on chip at the front end of the receiver with a resistance value that matches the channel impedance. Matching of impedance at the channel/receiver interface helps reduce the reflected signal energy back to the transmitter thus reducing noise and timing jitter of the signal and improving the return loss (RL).
Typically in a data channel, a terminated signal is AC coupled through a relatively large capacitance to an input buffer to condition the signal for further processing. Ideally, the AC coupling capacitance does not affect the termination impedance because it connects to an (ideally) infinite impedance buffer. In reality, however, there are parasitic capacitances that are on-chip, e.g., the terminal and Electrostatic Discharge (ESD) capacitance on one end of the AC coupling capacitor and the input buffer gate capacitance and AC coupling capacitance to ground that alter the termination impedance magnitude and phase.
These parasitic capacitances causes the high frequency components of the received digital signal to have a larger reflection magnitude thus worsening the return loss (RL). The parasitic capacitances must be reduced as much as possible while minimizing any change to the termination impedance to minimize the reflection and improve the RL figure.
It can be seen that there is a need for a method and apparatus for reducing parasitic capacitance.